Patent · US Active

Generating integrated circuit floorplan layouts

US8219959B2 · kind B2 · utility

6Cited by

11References

17Claims

0Family size

Assignee

LSI · US

Inventors

Juergen Dirks · Holzkirchen, DE
Norbert Mueller · Ostseebad Nienhagen, DE
Stefan G. Block · Munich, DE

Key dates

Filing date	Jul 24, 2009
Grant date	Jul 10, 2012
Priority date	—
Expiry date	Jul 27, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/392
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method of generating a floorplan layout of an integrated circuit (IC) that is amenable to implementation in a computer-aided design tool. The method is capable of performing placement and routing processing for the IC while requiring very little information about the specific circuitry used in various functional blocks of the IC. For example, at the time of the placement and routing processing, one or more functional blocks of the IC can be specified as empty functional blocks and/or functional blocks that are only partially rendered in gates.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.