Wafer backside grinding with stress relief
US8222118B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2008 |
| Grant date | Jul 17, 2012 |
| Priority date | — |
| Expiry date | Dec 15, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3065
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of relieving stress in a semiconductor wafer and providing a wafer backside surface finish capable of hiding cosmetic imperfections. Embodiments of the invention include creating a wafer backside surface which can be used for all dies on the semiconductor wafer intended for different product applications and be deposited with backside metallization (BSM) material. The method provides a rough texture on the wafer backside followed by isotropic etching of the wafer backside to recover the wafer strength as well as to preserve the rough texture of the wafer backside. After wafer backside metallization, the rough texture of the wafer backside hides cosmetic imperfections introduced by subsequent processes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.