Fiducial scheme adapted for stacked integrated circuits
US8222121B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 11, 2011 |
| Grant date | Jul 17, 2012 |
| Priority date | — |
| Expiry date | Jan 11, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for stacking integrated circuit substrates and the substrates used therein are disclosed. In the method, an integrated circuit substrate having top and bottom surfaces is provided. The substrate is divided vertically into a plurality of layers including an integrated circuit layer having integrated circuit elements constructed therein and a buffer layer adjacent to the bottom surface. An alignment fiducial mark extending from the top surface of the wafer into the substrate to a depth below that of the circuit layer is constructed. The vias are arranged in a pattern that provides a fiducial mark when viewed from the bottom surface of the substrate. The pattern can be chosen such that it is recognized by a commercial stepper/scanner/contact mask aligner when viewed from said backside of said wafer. After the substrate is thinned, the alignment fiducial mark is then used to position a mask used in subsequent processing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.