Packaged electronic devices having die attach regions with selective thin dielectric layer
US8222748B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 21, 2009 |
| Grant date | Jul 17, 2012 |
| Priority date | — |
| Expiry date | Dec 4, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19043
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A packaged electronic device including a package substrate having a top substrate surface including a die attach region including at least one land pad thereon and a first dielectric layer positioned lateral to the land pad and a non-die attach region. The non-die attach region includes a second dielectric layer, wherein a thickness of the second dielectric layer is>a thickness of the first dielectric layer by at least 5 μm. An IC die has a top semiconductor surface including active circuitry and at least one bonding conductor formed on the top semiconductor surface, and a bottom surface, wherein the bonding conductor of the IC die is joined to the land pad of the package substrate. An underfill layer is between the IC die and the die attach region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.