Power up circuit with low power sleep mode operation
US8222930B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 1, 2009 |
| Grant date | Jul 17, 2012 |
| Priority date | — |
| Expiry date | Jan 23, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY04S20/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A power up circuit that having reduced power consumption during power saving modes, while maintaining an active flag signal indicating that the power supply voltage is satisfactory. This is achieved by turning off the power up circuit during the power saving mode, and using a status holding circuit to maintain the active flag signal in response to the power down signal. The status holding circuit is responsive to an internal node of the power up circuit for generating the active flag signal when the internal node has reached a predetermined level. The power down signal can be one or both a sleep mode signal and a deep power down signal. The status holding comprises an override circuit for maintaining the active flag signal in the power saving mode, and a restore circuit for rapidly resetting at least the internal node of the power up circuit upon exit of the power saving mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.