Method and apparatus for a process, voltage, and temperature variation tolerant semiconductor device
US8222954B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 29, 2009 |
| Grant date | Jul 17, 2012 |
| Priority date | — |
| Expiry date | Feb 21, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00369
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus to reduce the degradation in performance of semiconductor-based devices due to process, voltage, and temperature (PVT) and/or other causes of variation. Adaptive feedback mechanisms are employed to sense and correct performance degradation, while simultaneously facilitating configurability within integrated circuits (ICs) such as programmable logic devices (PLDs). A voltage-feedback mechanism is employed to detect PVT variation and mirrored current references are adaptively adjusted to track and substantially eliminate the PVT variation. More than one voltage-feedback mechanism may instead be utilized to detect PVT-based variations within a differential device, whereby a first voltage-feedback mechanism is utilized to detect common-mode voltage variation and a second voltage-feedback mechanism produces mirrored reference currents to substantially remove the common-mode voltage variation and facilitate symmetrical operation of the differential device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.