Multiple level program verify in a memory device
US8223555B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 7, 2009 |
| Grant date | Jul 17, 2012 |
| Priority date | — |
| Expiry date | Jun 6, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods for multiple level program verify, memory devices, and memory systems are provided. In one such method, a series of programming pulses are applied to a memory cell to be programmed. A program verify pulse, at an initial program verify voltage, is applied to the memory cell after each programming pulse. The initial program verify voltage is a verify voltage that has been increased by a quick charge loss voltage. The quick charge loss voltage is subtracted from the initial program verify voltage after either a programming pulse has reached a certain reference voltage or a quantity of programming pulses has reached a pulse count threshold.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.