Integrated circuit and test method
US8225151B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 13, 2005 |
| Grant date | Jul 17, 2012 |
| Priority date | — |
| Expiry date | Nov 16, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5606
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit test controller and method defining a number N of failure events, applying the test to an integrated circuit under test by applying a predetermined sequence of input and output operations according to a test algorithm. Output data is compared to expected data, and a failure signal is generated when the output data does not correspond to the expected data. If a failure signal is generated, failure data related to the failure event is stored in a failure data register set. If the number N of failure events has been reached or if there are no more tests left, the content of the data failure register set is read out through a parallel failure data output port.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.