Method and apparatus for implementing a cyclic redundancy check circuit
US8225187B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2008 |
| Grant date | Jul 17, 2012 |
| Priority date | — |
| Expiry date | May 18, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cyclic redundancy check (CRC) bit-slice circuit including a plurality of AND gates coupled with configuration data is described. The configuration data may enable the plurality of AND gates to provide a set of CRC input data and feedback polynomial data meeting a plurality of CRC protocols. The CRC bit-slice circuit accepts a generator polynomial as an input design parameter to build a CRC module. The modularity of the design then allows a larger CRC design to be constructed from multiple CRC modules such that wider data width may be accommodated. Several CRC modules can be cascaded to accommodate various data widths and to meet a plurality of CRC protocols.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.