Integration of multiple gate oxides with shallow trench isolation methods to minimize divot formation

US8227318B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Max G. Levy · South Burlington, US
• Natalie B. Feilchenfeld · Jericho, US
• Richard A. Phelps · Colchester, US
• BethAnn Rainey · South Burlington, US
• James A. Slinkman · Montpelier, US
• Steven H. Voldman · South Burlington, US
• Michael J. Zierak · Colchester, US
• Hubert Enichlmair · Weinitzen, AT
• Martin Knaipp · Kufstein, AT
• Bernard Loeffler · Gleisdorf, AT
• Rainer Minixhofer · Kufstein, AT
• Jong Mun Park · Graz, AT
• Georg Roehrer · Lebring, AT

Key dates

• Filing date: Nov 19, 2009
• Grant date: Jul 24, 2012
• Expiry date: May 27, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76229
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method of forming an isolation region is provided that in one embodiment substantially reduces divot formation. In one embodiment, the method includes providing a semiconductor substrate, forming a first pad dielectric layer on an upper surface of the semiconductor substrate and forming a trench through the first pad dielectric layer into the semiconductor substrate. In a following process sequence, the first pad dielectric layer is laterally etched to expose an upper surface of the semiconductor substrate that is adjacent the trench, and the trench is filled with a trench dielectric material, wherein the trench dielectric material extends atop the upper surface of the semiconductor substrate adjacent the trench and abuts the pad dielectric layer.