Low lag transfer gate device
US8227844B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 14, 2008 |
| Grant date | Jul 24, 2012 |
| Priority date | — |
| Expiry date | Sep 4, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/8037
Abstract
A CMOS active pixel sensor (APS) cell structure includes at least one transfer gate device and method of operation. A first transfer gate device comprises a diodic or split transfer gate conductor structure having a first doped region of first conductivity type material and a second doped region of a second conductivity type material. A photosensing device is formed adjacent the first doped region for collecting charge carriers in response to light incident thereto, and, a diffusion region of a second conductivity type material is formed at or below the substrate surface adjacent the second doped region of the transfer gate device for receiving charges transferred from the photosensing device while preventing spillback of charges to the photosensing device upon timed voltage bias to the diodic or split transfer gate conductor structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.