Systems and methods for a continuous-well decoupling capacitor
US8227846B2 · kind B2 · utility
2Cited by
1References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 12, 2010 |
| Grant date | Jul 24, 2012 |
| Priority date | — |
| Expiry date | Jan 29, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/217
Abstract
A decoupling capacitor includes a pair of MOS capacitors formed in wells of opposite plurality. Each MOS capacitor has a set of well-ties and a high-dose implant, allowing high frequency performance under accumulation or depletion biasing. The top conductor of each MOS capacitor is electrically coupled to the well-ties of the other MOS capacitor and biased consistently with logic transistor wells. The well-ties and/or the high-dose implants of the MOS capacitors exhibit asymmetry with respect to their dopant polarities.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.