Method and structure of wafer level encapsulation of integrated circuits with cavity
US8227911B1 · kind B1 · utility
15Cited by
0References
12Claims
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Inventor
Key dates
| Filing date | Dec 9, 2009 |
| Grant date | Jul 24, 2012 |
| Priority date | — |
| Expiry date | Jun 3, 2030 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB81C1/00246
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
The present invention is related shielding integrated devices using CMOS fabrication techniques to form an encapsulation with cavity. The integrated circuits are completed first using standard IC processes. A wafer-level hermetic encapsulation is applied to form a cavity above the sensitive portion of the circuits using IC-foundry compatible processes. The encapsulation and cavity provide a hermetic inert environment that shields the sensitive circuits from EM interference, noise, moisture, gas, and corrosion from the outside environment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.