Patent · US Active

Circuit for biasing a well from three voltages

US8228115B1 · kind B1 · utility

2Cited by

4References

17Claims

0Family size

Assignee

XILINX, INC. · US

Inventor

Edward Cullen · Clane, IE

Key dates

Filing date	Jun 22, 2009
Grant date	Jul 24, 2012
Priority date	—
Expiry date	Sep 22, 2030

Classification

Technology area (CPC H)Electricity
CPC primaryH03K19/00315
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A biasing circuit of an integrated circuit includes a well of the integrated circuit and a plurality of transistors disposed in the well. The transistors couple the well to three signals providing corresponding voltages. The transistors bias the well to an extreme one of the corresponding voltages for the three signals.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.