Stacked semiconductor chip package with shared DLL signal and method for fabricating stacked semiconductor chip package with shared DLL signal
US8228704B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 26, 2008 |
| Grant date | Jul 24, 2012 |
| Priority date | — |
| Expiry date | May 26, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor chip package and a semiconductor chip fabricating method are provided. A semiconductor chip package comprises at least two semiconductor chips having a stacked configuration, the semiconductor chips at least one of: sharing DC signals of DC generating circuits provided by one of the semiconductor chips; and sharing a DLL clock signal of a DLL circuit provided by the semiconductor chip having the DC generating circuits or provided by another semiconductor chip. Power consumption can be reduced, and sharing a DLL clock is valid. In addition, a stabilized DC supply can be guaranteed and an increase for level trimming range and productivity can be improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.