Fused booth encoder multiplexer
US8229992B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 1, 2007 |
| Grant date | Jul 24, 2012 |
| Priority date | — |
| Expiry date | Jun 11, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3872
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiplier circuit comprises a fused Booth encoder multiplexer which produces partial product bits, a tree which uses the partial product bits to generate partial products, and an adder which uses the partial products to generate intermediate sum and carry results for a multiplication operation. The fused Booth encoder multiplexer utilizes encoder-selector cells having a logic tree which carries out a Boolean function according to a Booth encoding and selection algorithm to produce one of the partial product bits at a dynamic node, and a latch connected to the dynamic node which maintains the value at an output node. The encoder-selector cells operate in parallel to produce the partial product bits generally simultaneously. A given one of the encoder-selector cells has a unique set of both multiplier operand inputs and multiplicand operand inputs, and produces a single partial product bit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.