Method to test hold path faults using functional clocking
US8230283B2 · kind B2 · utility
5Cited by
9References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2009 |
| Grant date | Jul 24, 2012 |
| Priority date | — |
| Expiry date | Sep 29, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31725
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system and method for detecting hold path faults in an integrated circuit is provided in exemplary embodiments. These exemplary embodiments introduce a method of identifying data paths within an integrated circuit with statistically the highest timing slack among the data paths within the integrated circuit that cover the entire process space of the circuit. By identifying these paths (i.e., shortest data paths), a robust test pattern can be generated that directly tests for hold path faults on short data paths within the integrated circuit using one functional clock pulse.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.