Iterative decoder memory arrangement
US8230312B1 · kind B1 · utility
10Cited by
8References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 8, 2009 |
| Grant date | Jul 24, 2012 |
| Priority date | — |
| Expiry date | Apr 25, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6561
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present disclosure includes apparatus, systems and techniques relating to iterative decoder memory arrangement. In some implementations, an apparatus includes a memory module to communicate with an iterative code decoder. The memory module includes a single R memory component to store R data associated with a current codeword, and R data associated with a previous codeword. The memory module includes a Q memory component to store Q data associated with the current codeword, and Q data associated with the previous codeword. The memory module includes a channel detector memory component to store channel extrinsic information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.