Patent · US Active

Reliability enhancement of metal thermal interface

US8232636B2 · kind B2 · utility

5Cited by
25References
24Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJan 26, 2010
Grant dateJul 31, 2012
Priority date
Expiry dateOct 25, 2030

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L2224/73204
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

A frontside of a chip is bonded to a top surface of a chip carrier. Seal material is dispensed at a periphery of the top surface of the chip carrier. A solder TIM having a first side and a second side is provided. The first side of the TIM contacts a backside of the chip. A reflow is performed to melt the TIM. The second side of the TIM is bonded to a lid. The seal material is cured. The lid is attached to the top surface of the chip carrier. Backfill material is injected into a space between the top surface of the chip carrier and the lid. The backfill material abuts sides of the TIM. The backfill material is cured. TIM solder cracking and associated thermal degradation are mitigated.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.