Memory architecture and cell design employing two access transistors
US8233316B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 17, 2009 |
| Grant date | Jul 31, 2012 |
| Priority date | — |
| Expiry date | Oct 21, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8828
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved memory array architecture and cell design in which the cell employs two access transistors. In one embodiment, the two access transistors in each cell are coupled at one of their channel terminals to a memory element, which in turn is connected to a bit line. The other of the channel terminals are effectively tied together via reference lines. The word lines (i.e., gates) of the two access transistors are also tied together. The result in a preferred embodiment is a cell having two access transistors wired and accessed in parallel. With such a configuration, the widths of the access transistors can be made one-half the width of more-traditional one-access-transistor designs, saving layout space in that (first) dimension. Moreover, because the word lines of adjacent cells will be deselected, the improved design does not require cell-to-cell isolation (e.g., trench isolation) in the other (second) dimension. The result, when applied to a phase change memory, comprises about a 37% reduction in layout area from previous cell designs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.