Semiconductor memory device
US8233339B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 3, 2010 |
| Grant date | Jul 31, 2012 |
| Priority date | — |
| Expiry date | Jan 29, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2272
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes an open-loop-type delay locked loop (DLL) configured to generate a clock signal locked by reflecting a first delay amount which actually occurs in a data path and a second delay amount which is required for locking the clock signal, a latency control unit configured to shift an inputted command according to a latency code value corresponding to the first delay amount and latency information, and output the shifted command, and an additional delay line configured to delay the shifted command according to a delay code value corresponding to the second delay amount, and output the command of which operation timing is controlled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.