Devices comprising delay line for applying variable delay to clock signal
US8233579B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 2, 2007 |
| Grant date | Jul 31, 2012 |
| Priority date | — |
| Expiry date | Nov 12, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/7183
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The disclosure relates to a device comprising at least one delay line for applying a variable delay to a clock signal and a controller for controlling the variable delay of the delay line. Each delay line comprises a plurality of concatenated delay banks which provide different delay values with respect to each other, a bypass parallel over each of said the delay banks, and switching elements associated with each of the delay banks for selecting either the respective delay bank or the respective bypass. Each of the delay banks is provided with a delay bank status indicator for indicating propagation of the clock signal through the delay bank towards the controller. The controller is provided for taking the indicated propagation of the clock signal into account upon setting said switching elements. Devices according to this disclosure are, amongst other uses, suited for use in Ultra Wide Band (UWB) receiving or transmitting devices, in particular those devices, designed for low power consumption, by enabling power on and off switching of parts of such devices as analog to digital converters and integrators, during timing windows.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.