System and method of performing two's complement operations in a digital signal processor
US8234319B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 25, 2005 |
| Grant date | Jul 31, 2012 |
| Priority date | — |
| Expiry date | Jun 17, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/5442
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of completing a two's complement operation includes receiving a plurality of byte values and splitting the plurality of byte values into a first portion and a second portion. Further, the method includes inputting the first portion to a first segment of a first four-to-two compressor, performing a first four-to-two compression operation on the first portion to generate a first set of results having a first row and a second row that is offset one bit from the first row, and carrying in a first value of one to complete a first two's complement operation. The method also includes inputting the second portion to a second segment of a second four-to-two compressor and adding two values of one immediately to the right of the second portion in order to carry in a second value of one to the second portion to complete a second two's complement operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.