Method for fast estimation of lithographic binding patterns in an integrated circuit layout
US8234603B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 14, 2010 |
| Grant date | Jul 31, 2012 |
| Priority date | — |
| Expiry date | Jul 25, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a lithographic difficulty metric that is a function of an energy ratio factor that includes a ratio of hard-to-print energy to easy-to-print energy of the diffraction orders along an angular coordinate θi of spatial frequency space, an energy entropy factor comprising energy entropy of said diffraction orders along said angular coordinate θi, a phase entropy factor comprising phase entropy of said diffraction orders along said angular coordinate θi, and a total energy entropy factor comprising total energy entropy of said diffraction orders. The hard-to-print energy includes energy of the diffraction orders at values of the normalized radial coordinates r of spatial frequency space in a neighborhood of r=0 and in a neighborhood of r=1, and the easy-to-print energy includes energy of the diffraction orders located at intermediate values of normalized radial coordinates r between the neighborhood of r=0 and the neighborhood of r=1. The value of the lithographic difficulty metric may be used to identify patterns in a design layout that are binding patterns in an optimization computation. The lithographic difficulty metric may be used to design integrated…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.