Reduction of threshold voltage variation in transistors comprising a channel semiconductor alloy by reducing deposition non-uniformities
US8236654B2 · kind B2 · utility
1Cited by
3References
25Claims
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Key dates
| Filing date | Dec 14, 2009 |
| Grant date | Aug 7, 2012 |
| Priority date | — |
| Expiry date | Nov 4, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/01
Abstract
A threshold adjusting semiconductor material, such as a silicon/germanium alloy, may be provided selectively for one type of transistors on the basis of enhanced deposition uniformity. For this purpose, the semiconductor alloy may be deposited on the active regions of any transistors and may subsequently be patterned on the basis of a highly controllable patterning regime. Consequently, threshold variability may be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.