Method of fabricating a device using low temperature anneal processes, a device and design structure
US8236709B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2009 |
| Grant date | Aug 7, 2012 |
| Priority date | — |
| Expiry date | Oct 16, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0227
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a device using a sequence of annealing processes is provided. More particularly, a logic NFET device fabricated using a low temperature anneal to eliminate dislocation defects, method of fabricating the NFET device and design structure is shown and described. The method includes forming a stress liner over a gate structure and subjecting the gate structure and stress liner to a low temperature anneal process to form a stacking force in single crystalline silicon near the gate structure as a way to memorized the stress effort. The method further includes stripping the stress liner from the gate structure and performing an activation anneal at high temperature on device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.