Cell array of semiconductor memory device and a method of forming the same
US8237199B2 · kind B2 · utility
0Cited by
5References
9Claims
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Key dates
| Filing date | Aug 5, 2010 |
| Grant date | Aug 7, 2012 |
| Priority date | — |
| Expiry date | Sep 25, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cell array includes a semiconductor substrate including an active region comprising a first region, a second region, and a transition region, the second region being separated from the first region by the transition region, wherein a top surface of the second region is at a different level than a top surface of the first region. The cell array also includes a plurality of word lines crossing over the first region. The cell array also includes a selection line crossing over the active region, wherein at least a portion of the selection line is located over the transition region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.