CMOS devices incorporating hybrid orientation technology (HOT) with embedded connectors
US8237247B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 8, 2009 |
| Grant date | Aug 7, 2012 |
| Priority date | — |
| Expiry date | Dec 13, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D87/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates to complementary devices, such as n-FETs and p-FETs, which have hybrid channel orientations and are connected by conductive connectors that are embedded in a semiconductor substrate. Specifically, the semiconductor substrate has at least first and second device regions of different surface crystal orientations (i.e., hybrid orientations). An n-FET is formed at one of the first and second device regions, and a p-FET is formed at the other of the first and second device regions. The n-FET and the p-FET are electrically connected by a conductive connector that is located between the first and second device regions and embedded in the semiconductor substrate. Preferably, a dielectric spacer is first provided between the first and second device regions and recessed to form a gap therebetween. The conductive connector is then formed in the gap above the recessed dielectric spacer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.