System and method for providing alignment mark for high-k metal gate process
US8237297B2 · kind B2 · utility
0Cited by
5References
20Claims
0Family size
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Key dates
| Filing date | Jul 13, 2010 |
| Grant date | Aug 7, 2012 |
| Priority date | — |
| Expiry date | Oct 20, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76229
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
The alignment mark and method for making the same are described. In one embodiment, a semiconductor structure includes a substrate having a device region and an alignment region; a first shallow trench isolation (STI) feature in the alignment region and having a first depth D1; a second STI feature in the device region and having a second depth D2; an alignment mark with patterned features overlying the first STI in the alignment region; and a gate stack formed on an active region in the device region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.