Meng-Wei Chen
20Patents
4h-index
50Co-inventors
62Inventor score
Filing activity: Apr 18, 2003 → May 7, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8148232B2 | Overlay mark enhancement feature | Electricity | 13 | Active |
| US8822343B2 | Enhanced FinFET process overlay mark | Electricity | 11 | Active |
| US8850369B2 | Metal cut process flow | Electricity | 10 | Active |
| US7097945B2 | Method of reducing critical dimension bias of dense pattern and isolation pattern | Physics | 5 | Expired |
| US8455982B2 | Overlay mark enhancement feature | Electricity | 2 | Active |
| US9129974B2 | Enhanced FinFET process overlay mark | Electricity | 2 | Active |
| US10146141B2 | Lithography process and system with enhanced overlay quality | Physics | 2 | Active |
| US10073354B2 | Exposure method of wafer substrate, manufacturing method of semiconductor device, and exposure tool | Electricity | 2 | Active |
| US8203836B2 | Cover structure | Physics | 1 | Active |
| US8562843B2 | Integrated circuit method with triple patterning | Electricity | 1 | Active |
| US11003091B2 | Method of fabricating reticle | Electricity | 1 | Active |
| US8840796B2 | Integrated circuit method with triple patterning | Electricity | 1 | Active |
| US10461037B2 | Method for forming semiconductor device structure with overlay grating | Electricity | 1 | Active |
| US10534272B2 | Method of fabricating reticle | Electricity | 1 | Active |
| US8716139B2 | Method of patterning a semiconductor device | Electricity | 0 | Active |
| US9773671B1 | Material composition and process for mitigating assist feature pattern transfer | Physics | 0 | Active |
| US10734325B2 | Method for forming semiconductor device structure with overlay grating | Electricity | 0 | Active |
| US8237297B2 | System and method for providing alignment mark for high-k metal gate process | Electricity | 0 | Active |
| US11940737B2 | Method of fabricating reticle | Electricity | 0 | Active |
| US10867933B2 | Method for forming semiconductor device structure with overlay grating | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.