Implementing phase locked loop (PLL) with enhanced locking capability with a wide range dynamic reference clock
US8237510B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2010 |
| Grant date | Aug 7, 2012 |
| Priority date | — |
| Expiry date | Oct 28, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/103
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and a phase locked loop (PLL) circuit for implementing enhanced locking capability with a wide range dynamic reference clock, and a design structure on which the subject circuit resides are provided. The PLL circuit includes a Voltage Controlled Oscillator (VCO) and a plurality of filter comparators receiving a differential filter VCO control voltage. The plurality of filter comparators comparing the differential filter VCO control voltage values, provides a respective gate enable signal responsive to the compared differential filter VCO control voltage values. A clock signal is applied to an up/down counter responsive to the respective gate enable signal and the wide range dynamic reference clock. The count values of the up/down counter are provided to the VCO to select a respective frequency range for the VCO.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.