Dual port PLD embedded memory block to support read-before-write in one clock cycle
US8238191B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 14, 2010 |
| Grant date | Aug 7, 2012 |
| Priority date | — |
| Expiry date | Jan 14, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for a read-before-write functionality for a memory within a programmable logic device (PLD) is provided. The method begins when a read operation and a write operation are initiated through two different ports of a memory simultaneously to access the same address in the memory. In order to prevent the write operation from proceeding prior to the read operation, a read-before-write control logic is provided to the control block of the port that supports the write operation. Thus, the write operation is paused until the control block of the port that supports the write operation receives a signal from a read sense amplifier indicating that the read operation is complete. The read sense amplifier is capable of detecting the completion of a read operation by monitoring the voltage difference of the read bitline. When this voltage difference reaches a threshold value, the read sense amplifier triggers a write wordline signal. The enabling of the write wordline signal causes, the data to be written to the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.