Methods, systems, and apparatus for variation aware extracted timing models
US8239798B1 · kind B1 · utility
31Cited by
7References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2008 |
| Grant date | Aug 7, 2012 |
| Priority date | — |
| Expiry date | Aug 2, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment of the invention, a method of analysis of a circuit design is disclosed to generate a statistical timing model. The method includes receiving a timing graph of a circuit including arcs with a statistical function of delay, slew, or arrival time; determining primary input ports and output ports of the circuit; identifying timing pins between the input ports and the output ports of the circuit; and evaluating the timing pins from input ports to output ports to reduce the timing graph to ease analysis of the reduced timing graph with a processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.