Method for calculating capacitance gradients in VLSI layouts using a shape processing engine
US8239804B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2009 |
| Grant date | Aug 7, 2012 |
| Priority date | — |
| Expiry date | Jul 17, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Computing the gradients of capacitances in an integrated circuit chip layout with respect to design and process parameters is described. Included is a shape processing engine in the form of a variational mapping engine and a capacitance calculation engine that includes a gradient calculation engine. The variational mapping engine translates physical parameter variations into variations on the edges of the elementary patterns to which the layout of the integrated circuit is decomposed. The gradient calculation engine computes capacitance gradients by combining information from two sources. The first source consists of pre-existing gradients in a capacitance lookup table. The second source consists of analytical expressions of capacitance correction factors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.