Semiconductor integrated circuit test method
US8241926B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 23, 2010 |
| Grant date | Aug 14, 2012 |
| Priority date | — |
| Expiry date | Feb 19, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2896
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A wafer of semiconductor integrated circuits with wafer-level chip-scale packages is tested in two stages. The chip-scale packages include conductive posts extending through a sealing layer and capped by terminals. Measurements strongly affected by contact resistance are carried out before the terminals are formed, using a first probe card having probe pins that contact the ends of the conductive posts. Other measurements are carried out after the terminals are formed, using a second probe card having probe pins that contact the terminals. Accurate measurements can be made in this way even if the terminals are lead-free solder bumps with variable contact resistance. Fabrication yields are improved accordingly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.