System and method for providing low voltage high density multi-bit storage flash memory
US8241975B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 4, 2011 |
| Grant date | Aug 14, 2012 |
| Priority date | — |
| Expiry date | Aug 4, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
A system and method is disclosed for providing a low voltage high density multi-bit storage flash memory. A dual bit memory cell of the invention comprises a substrate having a common source, a first drain and first channel, and a second drain and a second channel. A common control gate is located above the source. A first floating gate and a second floating gate are located on opposite sides of the control gate. Each floating gate is formed with a sharp tip adjacent to the control gate and an upper curved surface that follows a contour of the surface of the control gate. The sharp tips of the floating gates efficiently discharge electrons into the control gate when the memory cell is erased. The curved surfaces increase capacitor coupling between the control gate and the floating gates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.