Inventor · Mechanicville, NY, US

Andre P. Labonte

56Patents

9h-index

43Co-inventors

78Inventor score

Filing activity: Dec 2, 2003 → May 13, 2024

Most-cited inventions

Patent	Title	Area	Cited by	Status
US10026824B1	Air-gap gate sidewall spacer and method	Electricity	31	Active
US9824921B1	Method and apparatus for placing a gate contact inside a semiconductor active region having high-k dielectric gate caps	Electricity	23	Active
US10243053B1	Gate contact structure positioned above an active region of a transistor device	Electricity	22	Active
US9490317B1	Gate contact structure having gate contact layer	Electricity	21	Active
US9691897B2	Three-dimensional semiconductor transistor with gate contact in active region	Electricity	20	Active
US9780178B2	Methods of forming a gate contact above an active region of a semiconductor device	Electricity	17	Active
US9397049B1	Gate tie-down enablement with inner spacer	Electricity	15	Active
US9929048B1	Middle of the line (MOL) contacts with two-dimensional self-alignment	Electricity	15	Active
US9941278B2	Method and apparatus for placing a gate contact inside an active region of a semiconductor	Electricity	12	Active
US8507375B1	Alignment tolerant semiconductor contact and method	Electricity	9	Active
US9324656B1	Methods of forming contacts on semiconductor devices and the resulting devices	Electricity	8	Active
US7968418B1	Apparatus and method for isolating integrated circuit components using deep trench isolation and shallow trench isolation	Electricity	7	Active
US9455254B2	Methods of forming a combined gate and source/drain contact structure and the resulting device	Electricity	7	Active
US9502286B2	Methods of forming self-aligned contact structures on semiconductor devices and the resulting devices	Electricity	6	Active
US9478662B2	Gate and source/drain contact structures for a semiconductor device	Electricity	6	Active
US9640625B2	Self-aligned gate contact formation	Electricity	6	Active
US8004032B1	System and method for providing low voltage high density multi-bit storage flash memory	Electricity	6	Active
US9947589B1	Methods of forming a gate contact for a transistor above an active region and the resulting device	Electricity	5	Active
US7175777B1	Method of forming a sub-micron tip feature	Electricity	5	Expired
US9570397B1	Local interconnect structure including non-eroded contact via trenches	Electricity	5	Active
US8580628B2	Integrated circuit contact structure and method	Electricity	4	Active
US10204994B2	Methods of forming a semiconductor device with a gate contact positioned above the active region	Electricity	4	Active
US7781295B1	System and method for providing a single deposition emitter/base in a bipolar junction transistor	Electricity	4	Active
US11112694B2	Methods of forming variable-depth device structures	Physics	4	Active
US10249728B2	Air-gap gate sidewall spacer and method	Electricity	3	Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.