Methods of removing noble metal-containing nanoparticles, methods of forming NAND string gates, and methods of forming integrated circuitry
US8242008B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 18, 2009 |
| Grant date | Aug 14, 2012 |
| Priority date | — |
| Expiry date | Jan 3, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Some embodiments include methods of removing noble metal-containing particles from over a substrate. The substrate is exposed to a composition that reduces adhesion between the noble metal-containing particles and the substrate, and simultaneously the substrate is spun to sweep at least some of the noble metal-containing particles off from the substrate. Some embodiments include methods in which tunnel dielectric material is formed across a semiconductor wafer. Metallic nanoparticles are formed across the tunnel dielectric material. A stack of two or more different materials is formed over the metallic nanoparticles. A portion of the stack is covered with a protective mask while another portion of the stack is left unprotected. The unprotected portion of the stack is removed to expose some of the metallic nanoparticles. The semiconductor wafer to is subjected to etchant suitable to undercut at least some of the exposed metallic nanoparticles, and simultaneously the semiconductor wafer is spun.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.