Mixed-gate metal-oxide-semiconductor varactors
US8242581B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 26, 2008 |
| Grant date | Aug 14, 2012 |
| Priority date | — |
| Expiry date | Jun 29, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/671
Abstract
Mixed gate varactors are provided. The mixed gate varactors may include a semiconductor region of a given doping type. A first terminal for the varactor may be formed from a gate structure on the semiconductor region. A second terminal for the varactor may be formed from a heavily doped region in the semiconductor region that has the same doping type as the given doping type. A third terminal for the varactor may be formed from a heavily doped region in the semiconductor region that has a different doping type than the given doping type. The gate structure may include multiple gate conductors on a gate insulator. The gate insulator may be a high-K dielectric. The gate conductors may be metals or other materials that have different work functions. A conductive layer such as a layer of polysilicon may electrically connect the first and second gate conductors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.