Clustered stacked vias for reliable electronic substrates
US8242593B2 · kind B2 · utility
4Cited by
4References
8Claims
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Key dates
| Filing date | Jan 27, 2008 |
| Grant date | Aug 14, 2012 |
| Priority date | — |
| Expiry date | Jul 10, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49222
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A substrate via structure for stacked vias in a substrate/chip assembly includes: a center via stack and a plurality of stacked vias clustered around the center via stack. In this structure, the center via and the surrounding vias are made of copper. Some of the surrounding vias may be non-functional vias and these may be of a different height than the functional vias.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.