Tamper resistant fuse design
US8242831B2 · kind B2 · utility
2Cited by
16References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2009 |
| Grant date | Aug 14, 2012 |
| Priority date | — |
| Expiry date | Jul 13, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A tamper resistant fuse design is generally presented. In this regard, an apparatus is introduced comprising a plurality of fuses in an integrated circuit device to store values and a plurality of resistors in parallel to the fuses, wherein each fuse includes a parallel resistor to provide a potential dissipation path around the fuse. Other embodiments are also described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.