Semiconductor apparatus and chip selection method thereof
US8243485B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2009 |
| Grant date | Aug 14, 2012 |
| Priority date | — |
| Expiry date | Feb 13, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/01033
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor apparatus having a plurality of stacked chips includes: a plurality of latch units, each of which is disposed in a corresponding one of the plurality of chips and is configured to latch a clock signal and a frequency-divided signal at mutually different points of time to generate an chip identification signal of the corresponding one of the plurality of chips; and a plurality of chip selection signal generating units, each of which is disposed in the corresponding one of the plurality of chips and is configured to compare the chip identification signal of the corresponding one of the plurality of chips with a chip selection identification signal to generate a chip selection signal of the corresponding one of the plurality of chips, wherein the chip selection signal is configured to enable the corresponding one of the plurality of chips when the chip identification signal matches the chip selection identification signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.