NAND memory programming method using double vinhibit ramp for improved program disturb
US8243522B2 · kind B2 · utility
7Cited by
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16Claims
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Key dates
| Filing date | Dec 24, 2009 |
| Grant date | Aug 14, 2012 |
| Priority date | — |
| Expiry date | Aug 25, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of applying an inhibit bias to an unselected word line when programming a NAND memory device is provided. The method may include ramping the inhibit bias to the unselected word line to a first predetermined voltage and ramping the inhibit bias to the unselected word line to a second predetermined voltage. Ramping of the inhibit bias to the unselected word line to a first predetermined voltage may occur until a boosted channel reaches a leakage limited saturation potential.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.