Memory device page buffer configuration and methods
US8243529B2 · kind B2 · utility
3Cited by
1References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 4, 2009 |
| Grant date | Aug 14, 2012 |
| Priority date | — |
| Expiry date | Oct 8, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3427
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory devices and methods are described that include communication circuitry between page buffers in a memory array. Examples include communication circuitry that provide status information of page buffers that are directly adjacent to a given page buffer. The exchanged information can be used to adjust a given page buffer to compensate for effects in directly adjacent data lines that are being operated at the same time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.