Optimizing EDRAM refresh rates in a high performance cache architecture
US8244972B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 24, 2010 |
| Grant date | Aug 14, 2012 |
| Priority date | — |
| Expiry date | Jan 5, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0855
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Controlling refresh request transmission rates in a cache comprising: a refresh requestor configured to transmit a refresh request to a cache memory at a first refresh rate, the first refresh rate comprising an interval, the interval comprising receiving a plurality of first signals, the first refresh rate corresponding to a maximum refresh rate, and a refresh counter operatively coupled to the refresh requestor and configured to reset in response to receiving a second signal, increment in response to receiving each of a plurality of refresh requests from the refresh requestor, and reset and transmit a current count to the refresh requestor in response to receiving a third signal, wherein the refresh requestor is configured to transmit a refresh request at a second refresh rate, in response to receiving the current count from the refresh counter and determining that the current count is greater than a refresh threshold.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.