Store performance in strongly ordered microprocessor architecture
US8244985B2 · kind B2 · utility
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26References
20Claims
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Key dates
| Filing date | Jan 27, 2009 |
| Grant date | Aug 14, 2012 |
| Priority date | — |
| Expiry date | May 25, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus and methods relating to store operations are disclosed. In one embodiment, a first storage unit is to store data. A second storage unit is to store the data only after it has become detectable by a bus agent. Moreover, the second storage unit may store an index field for each data value to be stored within the second storage unit. Other embodiments are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.