Data storage and access in multi-core processor architectures
US8244986B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 30, 2009 |
| Grant date | Aug 14, 2012 |
| Priority date | — |
| Expiry date | Sep 22, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/082
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Technologies are generally described for a system for sending a data block stored in a cache. In some examples described herein, a system may comprise a first processor in a first tile. The first processor is effective to generate a request for a data block, the request including a destination identifier identifying a destination tile for the data block, the destination tile being distinct from the first tile. Some example systems may further comprise a second tile effective to receive the request, the second tile effective to determine a data tile including the data block, the second tile further effective to send the request to the data tile. Some example systems may still further comprise a data tile effective to receive the request from the second tile, the data tile effective to send the data block to the destination tile.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.