Power gating processor execution units when number of instructions issued per cycle falls below threshold and are independent until instruction queue is full

US8245065B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Tim Niggemeier · Laatzen, DE
• Harry Barowski · Balingen, DE
• Maarten J. Boersma · Holzgerlingen, DE
• Gunnar Spiess · Balingen, DE

Key dates

• Filing date: Mar 4, 2009
• Grant date: Aug 14, 2012
• Expiry date: Jan 1, 2031

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F9/3871
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A method of power gating a microprocessor having an instruction scheduling unit for receiving issued instructions from an instruction decode unit; an execution unit coupled to receive and send signals from and to the instruction scheduling unit; and a state machine located within the execution unit, the method comprises: obtaining a number of instructions per cycle being issued to the instruction scheduling unit; determining, subsequent to obtaining the number of instructions per cycle, if the number of instruction per cycle being issued to the instruction scheduling unit is less than a threshold level, and then determining if at least two of the instructions being issued to the instruction scheduling unit are independent of each other only when the instructions per cycle is less than the threshold level; determining when at least two of the instructions being issued to the instruction scheduling unit are independent of each other; and power gating the microprocessor to gate off power to idle macros with a signal from the state machine when the instructions are independent of each other without incurring significant loss of performance until an issue queue in the instruction schedu…