Multi-bit memory error management
US8245087B2 · kind B2 · utility
9Cited by
26References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2007 |
| Grant date | Aug 14, 2012 |
| Priority date | — |
| Expiry date | Aug 11, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various embodiments include fault tolerant memory apparatus, methods, and systems, including an apparatus comprising a memory device including a plurality of addressable memory locations, and a memory manager coupled to the memory device, the memory manager including a scheduling unit operable to detect a multi-bit error in data read from the memory device, and to retry the read operation in order to distinguish between an intermittent error and a persistent error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.