Error checking and correction (ECC) system and method
US8245109B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2006 |
| Grant date | Aug 14, 2012 |
| Priority date | — |
| Expiry date | Oct 4, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1806
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method stores data and check bits for that data within a memory chip. The memory chip stores the data and check bits in a plurality of pages contained in the memory chip, each page including a plurality of storage locations with each storage location having an associated address. The method includes receiving data to be stored in the memory, calculating check bits for the received data, mapping the data to addresses associated with the storage locations in a given page in the memory chip, mapping the check bits to addresses associated with the storage locations contained in the same page as the data, and storing the data and check bits in the page. The method may be applied to a single memory chip or to multiple memory chips.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.